Publications
2023
Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
Kathleen Feng, Taeyoung Kong, Kalhan Koul, Jackson Melchert, Alex
Carsello, Qiaoyi Liu, Gedeon Nyengele, Maxwell Strange, Keyi Zhang,
Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen,
Nikhil Bhagdikar, Zach A Myers, Brandon D'Agostino, Pranil Joshi,
Stephen Richardson,
IEEE Journal of Solid-State Circuits (JSSC), September 2023
- DOI -
Building First-Order Energy Modeling Intuition in Computer Architecture Lectures
Workshop on Computer Architecture Education (WCAE) co-located with ISCA, June 2023
A Fast Open-Source Extended GCD Accelerator
Kavya Sreedhar, Mark Horowitz,
Workshop on Open-Source Computer Architecture Research (OSCAR) co-located with ISCA, June 2023
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains
Ankita Nayak, Keyi Zhang, Raj Setaluri, Alex Carsello, Makai Mann,
ACM Transactions on Reconfigurable Technology and Systems (TRETS), April 2023
- DOI -
2022
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
Jackson Melchert*, Keyi Zhang*, Yuchen Mei, Mark Horowitz,
(* = denotes equal contribution)
Workshop on Democratizing Domain-Specific Accelerators (WDDSA) co-located with MICRO, October 2022
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Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays
Taeyoung Kong, Kalhan Koul, Priyanka Raina, Mark Horowitz,
Workshop on Democratizing Domain-Specific Accelerators (WDDSA) co-located with MICRO, October 2022
- PDF -
A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion
Kavya Sreedhar, Mark Horowitz, and
Conference on Cryptographic Hardware and Embedded Systems (CHES), September 2022
mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design
Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark
Horowitz, Priyanka Raina, and
ACM/IEEE Design Automation Conference (DAC), July 2022
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
Kalhan Koul, Jackson Melchert, Kavya Sreedhar, Leonard Truong,
Gedeon Nyengele, Keyi Zhang, Qiaoyi Liu, Jeff Setter, Po-Han Chen,
Yuchen Mei, Maxwell Strange, Ross Daly, Caleb Donovick, Alex Carsello,
Taeyoung Kong, Kathleen Feng, Dillon Huff, Ankita Nayak, Rajsekhar
Setaluri, James Thomas, Nikhil Bhagdikar, David Durst, Zachary Myers,
Nestan Tsiskaridze, Stephen Richardson, Rick Bahr, Kayvon Fatahalian,
Pat Hanrahan, Clark Barrett, Mark Horowitz,
ACM Transactions on Embedded Computing Systems (TECS), July 2022
- DOI -
Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration
Kathleen Feng, Alex Carsello, Taeyoung Kong, Kalhan Koul, Qiaoyi
Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang,
Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen,
Nikhil Bhagdikar, Zachary Myers, Brandon D’Agostino, Pranil Joshi,
Stephen Richardson, Rick Bahr,
Symposium on High Performance Chips (Hot Chips), August 2022
- DOI -
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi
Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang,
Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen,
Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi,
Stephen Richardson, Rick Bahr,
IEEE VLSI Symposium on Technology and Circuits (VLSI), June 2022
- DOI - Best Demo Paper Award -
2021
Enabling Reusable Physical Design Flows with Modular Flow Generators
Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark
Horowitz, Priyanka Raina, and
Preprint, November 2021
Ultra-Elastic CGRAs for Irregular Loop Specialization
International Symposium on High-Performance Computer Architecture (HPCA), February 2021
2020
Creating An Agile Hardware Design Flow
Rick Bahr, Clark Barrett, Nikhil Bhagdikar, Alex Carsello, Ross
Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng,
Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik
Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert,
Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen
Richardson, Raj Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell
Strange, James Thomas,
ACM/IEEE Design Automation Conference (DAC), July 2020
2019
Software, Architecture, and VLSI Co-Design for Fine-Grain Voltage and Frequency Scaling
PhD Thesis, December 2019
Evaluating Celerity: A 16nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie,
IEEE Solid-State Circuits Letters, December 2019
PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks
Cheng Tan, Yanghui Ou, Shunning Jiang, Peitian Pan,
IEEE International Conference on Computer Design (ICCD), November 2019
A 1.4 GHz 695 Giga RISC-V Inst/s 496-core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie,
IEEE Symposium on VLSI Circuits (VLSIC), June 2019
2018
An Open-Source Python-Based Hardware Generation, Simulation, and Verification Framework
Shunning Jiang,
Workshop on Open-Source EDA Technology (WOSET) co-located with ICCAD, November 2018
A New Era of Silicon Prototyping in Computer Architecture Research
RISC-V Day Workshop co-located with MICRO, October 2018
A Modular Digital VLSI Flow for High-Productivity SoC Design
Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason
Clemons, Joel Emer, Matthew Fojtik, Alicia Klinefelter, Michael
Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath,
ACM/IEEE Design Automation Conference (DAC), June 2018
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
Scott Davidson, Shaolin Xie,
IEEE Micro – Special issue for top picks from Hot Chips 29, March/April 2018
2017
Four Monolithically Integrated Switched-Capacitor DC-DC Converters with Dynamic Capacitance Sharing in 65-nm CMOS
Ivan Bukreyev,
IEEE Transactions on Circuits and Systems I (TCAS I), November 2017
Using Intra-Core Loop-Task Accelerators to Improve the Productivity and Performance of Task-Based Parallel Programs
Ji Kim, Shunning Jiang,
IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2017
Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott
Davidson, Paul Gao, Gai Liu, Anuj Rao, Austin Rovinski, Ningxiao Sun,
Workshop on Computer Architecture Research with RISC-V (CARRV) co-located with MICRO, October 2017
- PDF - Slides - Open-Source Code - Site -
Celerity: An Open Source RISC-V Tiered Accelerator Fabric
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott
Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao,
Austin Rovinski, Loai Salem, Ningxiao Sun,
Symposium on High Performance Chips (Hot Chips), August 2017
- Slides - Open-Source Code -
2016
Experiences Using A Novel Python-Based Hardware Modeling Framework For Computer Architecture Test Chips
Poster and Abstract at Symposium on High Performance Chips (Hot Chips), August 2016
Asymmetry-Aware Work-Stealing Runtimes
ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2016
2014
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks
Waclaw Godycki*,
(* = denotes equal contribution)
IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2014