University of Southern California, Electrical and Computer Engineering
ctorng [at] usc [.] edu
I am an assistant professor in the ECE department at the University of Southern California. Previously, I was a postdoctoral researcher at Stanford University working with Mark Horowitz in the Stanford AHA Agile Hardware Project. During my PhD, I was advised by Christopher Batten at Cornell University. I am a computer architect with an emphasis on agile hardware design and rapid chip prototyping. I build complex digital systems-on-chip (SoCs) for applications in image processing and machine learning. My work involves aspects of co-design across both software and hardware.
It is challenging today for traditional hardware design flows to produce high-quality designs quickly and at low cost. We have just experienced a global chip shortage with significant economic impacts, and it is now critically important to ask new research questions regarding how architectures and systems can be designed from the ground up to reduce the end-to-end design effort across the software-hardware stack, rather than designing primarily for higher performance and efficiency. My research approach tackles this problem from the system aspects down through to the silicon implementation.
I have a demonstrated track record in building digital silicon prototypes that support my research, including an end-to-end agile flow with compiler-accelerator co-design (Amber SoC in 16nm), productive chip building methodologies (Celerity SoC in 16nm), silicon-validation of a new Python-embedded hardware description language called PyMTL (BRGTC1 in 130nm, BRGTC2 in 28nm), evaluating fine-grain power control techniques (DCS in 65nm), and hardware-accelerated advanced cryptography (CryptoVDF in 130nm). My activities have resulted in a selection as a Rising Star in Computer Architecture by Georgia Tech (2018) and an IEEE Micro Top Pick from Hot Chips (2018).